Skip to content

Supported CPUID Instruction Set Codes

CPUID Instruction Set Codes Supported by VM Instances

  • fpu: Onboard FPU (floating point support)
  • eagerfpu: Non lazy FPU restore
  • vme: Virtual 8086 mode enhancements
  • de: Debugging Extensions (CR4.DE)
  • smx: Safer mode: TXT (TPM support)
  • pse: Page Size Extensions (4MB memory pages)
  • tsc: Time Stamp Counter (RDTSC)
  • constant_tsc: TSC ticks at a constant rate
  • nonstop_tsc: TSC does not stop in C states
  • ptsc: performance time-stamp counter
  • msr: Model-Specific Registers (RDMSR, WRMSR)
  • nodeid_msr: NodeId MSR
  • pae: Physical Address Extensions (support for more than 4GB of RAM)
  • mce: Machine Check Exception
  • cx8: CMPXCHG8 instruction (64-bit compare-and-swap)
  • apic: Onboard APIC
  • x2apic: x2APIC
  • extapic: Extended APIC space
  • sep: SYSENTER/SYSEXIT
  • mtrr: Memory Type Range Registers
  • k6_mtrr: AMD K6 nonstandard MTRRs
  • pge: Page Global Enable (global bit in PDEs and PTEs)
  • mca: Machine Check Architecture
  • smca: Scalable MCA
  • cmov: CMOV instructions (conditional move) (also FCMOV)
  • pat: Page Attribute Table
  • pse36: 36-bit PSEs (huge pages)
  • clflush: Cache Line Flush instruction
  • mmx: Multimedia Extensions
  • cxmmx: Cyrix MMX extensions
  • fxsr: FXSAVE/FXRSTOR, CR4.OSFXSR
  • sse: Intel SSE vector instructions
  • misalignsse: indicates if a general-protection exception (#GP) is generated when some legacy SSE instructions operate on unaligned data. Also depends on CR0 and Alignment Checking bit
  • sse2: SSE2
  • ss: CPU self snoop
  • syscall: SYSCALL (Fast System Call) and SYSRET (Return From Fast System Call)
  • nx: Execute Disable
  • pdpe1gb: One GB pages (allows hugepagesz=1G)
  • rdtscp: Read Time-Stamp Counter and Processor ID
  • lm: Long Mode (x86-64: amd64, also known as Intel 64, i.e. 64-bit capable)
  • lahf_lm: Load AH from Flags (LAHF) and Store AH into Flags (SAHF) in long mode
  • constant_tsc: TSC ticks at a constant rate
  • rep_good: rep microcode works well
  • nopl: The NOPL (0F 1F) instructions
  • eagerfpu: Non lazy FPU restore
  • pni: SSE-3 (“Prescott New Instructions”)
  • pclmulqdq: Perform a Carry-Less Multiplication of Quadword instruction — accelerator for GCM)
  • ssse3: Supplemental SSE-3
  • fma: Fused multiply-add
  • cx16: CMPXCHG16B
  • pcid: Process Context Identifiers
  • invpcid: Invalidate Processor Context ID
  • sse4_1: SSE-4.1
  • sse4_2: SSE-4.2
  • x2apic: x2APIC
  • movbe: Move Data After Swapping Bytes instruction
  • popcnt: Return the Count of Number of Bits Set to 1 instruction (Hamming weight, i.e. bit count)
  • tsc_deadline_timer: Tsc deadline timer
  • xsave: Save Processor Extended States: also provides XGETBY,XRSTOR,XSETBY
  • avx: Advanced Vector Extensions
  • f16c: 16-bit fp conversions (CVT16)
  • rdrand: Read Random Number from hardware random number generator instruction
  • hypervisor: Running on a hypervisor
  • lahf_lm: Load AH from Flags (LAHF) and Store AH into Flags (SAHF) in long mode
  • abm: Advanced Bit Manipulation
  • fsgsbase: {RD/WR}{FS/GS}BASE instructions
  • bmi1: 1st group bit manipulation extensions
  • avx2: AVX2 instructions
  • smep: Supervisor Mode Execution Protection
  • bmi2: 2nd group bit manipulation extensions
  • erms: Enhanced REP MOVSB/STOSB
  • invpcid: Invalidate Processor Context ID
  • xsaveopt: Optimized XSAVE